Operating System Slides 📂 Introduction · 16 of 22 46 min read

Memory Segmentation in OS: Address Translation, Protection & Sharing

Master memory segmentation — the model that maps memory to how programmers think. Learn the two-part <s, d> logical address, the segment table with STBR/STLR, MMU address translation, per-segment R/W/X protection, library sharing across processes, and external fragmentation — with animated diagrams and two worked numericals.

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Memory Segmentation — Address Translation, Protection & Sharing

The memory model that matches how programmers actually think — code, data, stack and heap as separate, named segments. See how a two-part <s, d> address becomes a physical one, how per-segment permissions stop attacks, and how one library serves many processes. With fully animated diagrams and worked numericals.
<s, d> Translation Protection Bits Segment Sharing 2 Numericals
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SECTION 01

Why Segmentation Feels Natural

📚 REAL-WORLD ANALOGY · THE UNIVERSITY LIBRARY
A Library Is Not One Long Shelf
Walk into a library and you don't see a single undivided wall of books — you see sections: Fiction, Reference, Periodicals, Archives. Each section has its own size, its own rules (Reference is read-only, Archives are restricted), and can grow independently. You navigate by section + shelf number, never by a raw distance from the front door. Segmentation gives memory that same structure.
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The Programmer's Mental Model

You never think of your program as one flat array of bytes. You think in units: "the code", "the stack", "this array", "the sqrt routine". Segmentation lets the hardware see memory the same way — as a collection of variable-length, individually-protected, independently-growable pieces, each addressed by a segment number and an offset inside it.

SECTION 02 · DIAGRAM

The User's View — Memory as Segments

Logical View (program) Physical RAM (scattered) Seg 0 · CodeR + X Seg 1 · DataR + W Seg 2 · Heap ↑R + W · grows up Seg 3 · Stack ↓R + W · grows down Code · base 1400 Stack · base 3200 Data · base 4300 Heap · base 4700
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Same Segments, Scattered in RAM

The program sees an orderly list of segments; physical memory holds each one wherever a free hole was found — in a different order, with gaps between. The segment table is the map that ties the two views together, one row per segment.

SECTION 03 · DIAGRAM

The Logical Address — <s, d>

s segment number d offset within segment one logical address Picks the row indexes the segment table: table[s] → base, limit, perms Distance inside it must satisfy 0 ≤ d < limit, physical = base + d
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Two Numbers, Not One

Unlike a flat linear address, a segmented address is a pair. The segment number s says which region; the offset d says how far into it. The hardware never lets d escape its segment — that single check is what makes protection so cheap.

SECTION 03 · DIAGRAM

The Segment Table & Its Registers

STBR table's base address STLR = 5 number of segments Segment Table segbaselimitperm 014001000R X 16300400R W 24300400R X 332001100R W 447001000R W
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One Row Per Segment · Two Guard Registers

Each row holds a base, a limit and permission bits. STBR tells the MMU where this process's table lives (reloaded on every context switch); STLR holds how many segments exist, so a bogus segment number s ≥ STLR traps before any lookup.

SECTION 04 · DIAGRAM

Address Translation — The MMU at Work

CPUlogical <s, d> Segment Tablerow s → base, limitcheck d < limit ?and s < STLR Physical RAMbase + d yes ✓ 🛑 TRAP → OS (no)
⚙️
Two Reads, One Verdict

Every memory reference costs two accesses: one to fetch the descriptor (base, limit) and one for the data itself. The hardware validates s < STLR and d < limit; pass both and it emits base + d, fail either and it raises a trap. A TLB caches recent descriptors so the extra read nearly vanishes.

SECTION 04 · WORKED

Translating <2, 53> Step by Step

logical< 2 , 53 > table[2]base 4300 · limit 400 check53 < 400 ✓ physical4300 + 53 = 4353
AddressCheck (d < limit)Result
<2, 53>53 < 400 ✓4300 + 53 = 4353
<0, 1200>1200 < 1000 ✗TRAP — offset too big
<7, 0>7 ≥ STLR (5)TRAP — no such segment
SECTION 05 · DIAGRAM

Protection — Bits That Stop Attacks

Seg 0 · CODER + X (not W)base 1400 · limit 1000 Seg 1 · DATAR + W (not X)base 6300 · limit 400 Read codeallowed ✓ Write code🛑 TRAP Exec data🛑 TRAP (NX) Write dataallowed ✓
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Why Data Is Non-Executable

Marking the data and stack segments non-executable (the NX bit, sold as DEP on Windows and W^X on BSD) means an attacker who smuggles code into a buffer can't run it — the CPU traps the moment execution jumps there. The same descriptor that translates the address also enforces the permission, so the check is free.

SECTION 06 · DIAGRAM

Sharing — One Library, Many Processes

Process 1 tableseg 0 main → 1200seg 1 sqrt → 6300 Process 2 tableseg 0 main → 5000seg 1 sqrt → 6300 Shared sqrt (one copy)base 6300 · limit 400R + X · read-only
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Point the Same Base — Save the RAM

Both processes keep a sqrt row in their own table, and both rows carry the same base (6300). There is exactly one physical copy of the library; 50 processes sharing a 400 KB libc cost 400 KB total, not 20 MB. Because the shared segment is read-only (R+X), no process can corrupt it for the others.

SECTION 07 · DIAGRAM

The Catch — External Fragmentation

Physical memory Seg A · 200 free · 150 Seg B · 300 free · 120 Seg C · 250 free · 180 total free = 450, largest hole = 180 New Seg · 400needs 400 contiguous🛑 no single hole fits
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450 KB Free — Yet 400 Won't Fit

Because each segment needs a single contiguous region, free space scattered into holes of 150, 120 and 180 can't hold a 400 KB segment even though 450 KB is free in total. Segmentation cures internal fragmentation (segments are exact-sized) but keeps external fragmentation — which is why real systems pair it with paging.

NUMERICAL 1

Six Translations, One Segment Table

Segment table — 0: base 219, limit 600 · 1: 2300 / 14 · 2: 90 / 100 · 3: 1327 / 580 · 4: 1952 / 96. STLR = 5.

Logical <s, d>ValidationPhysical address
<0, 430>430 < 600 ✓219 + 430 = 649
<1, 10>10 < 14 ✓2300 + 10 = 2310
<2, 500>500 < 100 ✗TRAP — offset > limit
<3, 400>400 < 580 ✓1327 + 400 = 1727
<4, 112>112 < 96 ✗TRAP — offset > limit
<5, 20>5 ≥ STLR (5)TRAP — no such segment
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Three Valid, Three Trapped

Only 649, 2310 and 1727 are legal physical addresses. Two attempts overran their segment's limit, and one named a segment that doesn't exist — each caught by the same two guards, s < STLR and d < limit.

NUMERICAL 2

Boundary Cases That Trip Students

Segment table — 0: base 1200, limit 500 · 1: 2400 / 200 · 2: 0 / 800 · 3: 3200 / 400.

Logical <s, d>ValidationPhysical address
<0, 222>222 < 500 ✓1200 + 222 = 1422
<1, 199>199 < 200 ✓2400 + 199 = 2599
<2, 800>800 < 800 ✗TRAP — limit is exclusive
<3, 50>50 < 400 ✓3200 + 50 = 3250
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The Off-by-One That Matters

A valid offset runs 0 to limit − 1. So <1, 199> is the very last legal byte of segment 1, while <2, 800> traps — the offset must be strictly less than the limit. Segment 2 starting at base 0 is legal too: a base of zero is just a segment placed at the bottom of RAM.

SECTION 10

Segmentation vs Paging

AspectSegmentationPaging
Block sizeVariable — one per segmentFixed — one page (≈ 4 KB)
Programmer visibilityYes — natural unitsInvisible
Address form<s, d> — two-part<p, d> — transparent
External fragmentationYesNo
Internal fragmentationNoneUp to one page
Sharing granularityWhole segmentsIndividual pages
Protection granularityPer-segmentPer-page
Table sizeSmall (few rows)Large (millions)
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The Winner Is: Both

Segmentation gives meaning and protection; paging gives fragmentation-free placement. Modern CPUs use segmentation with paging — a program is split into logical segments, and each segment is then paged into fixed frames. You keep the programmer's model and lose external fragmentation.

SECTION 11

Segmentation in the Real World

🖥️
Intel x86 Protected Mode
GDT / LDT · since 1982
The Global and Local Descriptor Tables are literal segment tables — each descriptor carries base, limit and permission bits, enforced in hardware.
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Shared Libraries
libc.so · Windows DLLs
One physical copy of a shared object is mapped into many processes — exactly the segment-sharing trick, saving enormous RAM.
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Buffer-Overflow Defence
NX bit · DEP · W^X
Non-executable data and stack segments stop injected shellcode from running — permission bits doing security work.
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Multics
1965 · the pioneer
The system that introduced segmented virtual memory and inspired everything that followed, including Unix's rejection of it for simplicity.
☕
JVM Memory Areas
Method Area · Heap
The Java runtime carves memory into logical regions with distinct roles and lifetimes — a segment-like conceptual split.
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Kernel vs User Space
Ring 0 · Ring 3
Privilege levels attached to memory regions keep user code from touching kernel segments — protection granularity in action.
SECTION 12

Eight Rules for Segmentation

🧩 SEGMENTATION · CHECKLIST
1
A logical address is a pair <s, d> — segment number and offset — never a single flat number.
2
Each process owns a segment table: one row of base, limit and permission bits per segment.
3
Two guards on every access: s < STLR and d < limit; then physical = base + d.
4
Permission bits (R/W/X) enforce that code isn't writable and data isn't executable — the NX defence.
5
Sharing is trivial: point two tables' rows at the same base for one physical copy of a library.
6
Variable-length segments cause external fragmentation — contiguous placement, so compaction may be needed.
7
Each reference costs two memory reads (descriptor + data); a TLB caches descriptors.
8
Real systems combine segmentation + paging — the programmer's model without external fragmentation.
FINAL

Memory That Matches Your Mind

<s, d>Two-part address
base + dTranslation formula
R / W / XPer-segment guards
1 copyShared libraries
ExternalFragmentation cost
🎯
You Now Understand Segmentation

From the two-part address and the segment table, through MMU translation, protection bits and library sharing, to external fragmentation and the segmentation-vs-paging trade-off — you can translate any <s, d> by hand and explain why the model still lives inside every modern CPU.

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Where To Go Next

Segmentation solves meaning; paging solves placement. Next comes paging in depth — page tables, the TLB and multi-level tables — and then how segmentation and paging combine to build virtual memory.

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